The present invention is related to delay line technology, and more particularly to a discrete delay line architecture with wide delay range, fine granularity and small minimum delay.
Delay lines serve a variety of functions within digital systems. They can be used, for instance, to deskew a clock or to change the phase of a clock or of a signal.
To date, a variety of approaches have been used to add delay to a signal. Delay has been implemented using delay lines external to the integrated circuit. Such an approach, however, consumes pins and real estate both on the integrated circuit and on the circuit board.
Conventional Delay Locked Loops (DLLs) have also been used. DLLs, however, limit flexibility. That is, only a limited number of delay choices can be provided, and the choices must be determined at design time.
Discrete delay lines have also been implemented directly on the integrated circuit. Under such an approach, standard cell or other ASIC technology is used to implement the delay line. The integrated circuit approach to discrete delay lines is advantageous in that regular ASIC design and verification tools can be used to design and test the delay line. Delay lines designed using this approach, however, can exhibit variation in delay as the operating environment (e.g., temperature, voltage level, etc.) changes. In addition, since the delay line is implemented directly on an integrated circuit, it can exhibit changes in delay due to variations in the integrated circuit manufacturing process.
To date, discrete delay lines have taken the form of either linear discrete delay line architectures or binary weighted delay lines. Linear weighted delay lines offer small minimum delay, relatively coarse granularity, and have an inefficient area function. The granularity can be improved, but at the expense of increasing minimum delay.
On the other hand, binary weighted delay lines have large delay range, efficient area functions, excellent linearity, fine granularity, and relatively large minimum delay. Binary weighted delay lines can, however, cause large temporary glitches in the signal or clock being delayed when the binary control code switches at carry boundaries. What is needed is a delay line architecture having a wide delay range, a small minimum delay and fine granularity. In addition, what is needed is a delay line which has large maximum delays and fine granularity but which operates glitch-free when the delay line is switched to a different delay parameter.
According to one aspect of the present invention, a composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.
According to another aspect of the present invention, a delay line includes a multiplexer having a first and a second input, a binary weighted delay line connected to the first input and a linear discrete delay line connected to the second input. The binary weighted delay line includes an input and binary control means for controlling delay. The linear discrete delay line includes an input and linear control means for controlling delay. Control logic connected to the binary control means selects a delay through the binary weighted delay line. Control logic connected to the linear control means selects a delay through the linear discrete delay line. Control logic connected to the multiplexer selects between the output of the binary weighted delay line and the linear discrete delay line.
According to yet another aspect of the present invention, a system and method of delaying a signal is described The delay system includes a first and a second delay line. A signal is received and a first delayed signal is formed by passing the signal through the first delay line. A second delayed is signal also formed by passing the signal through the second delay line. One of the first and second delayed signals is selected and driven as the selected delayed signal.
According to yet another aspect of the present invention, a system and method is described for suppressing glitches in the output signal of a binary weighted delay system having first and second binary weighted delay lines. A first delayed signal is formed by passing the signal through the first binary weighted delay line. A second delayed signal is formed by passing the signal through the second binary weighted delay line. The first delayed signal is driven as the output signal. When the system determines that a change in delay is needed, delay is changed first in the second binary weighted delay line. The system waits for a predetermined period of time and then drives the second delayed signal as the output signal.